1. Field of the Invention
The present invention relates to a logic synthesis device and a logic synthesis method for performing logic synthesis and layout on an LSI (Large Scale Integration) circuit design.
2. Description of the Related Art
An LSI circuit design technique includes a process of logic synthesis, and, for a part having the large number of fan-out, buffering is performed for the purpose of load sharing. Then, a layout process is proceeded to.
Moreover, in the process of logic synthesis, a high drive cell is mapped onto a part where improvement in speed of processing timing is desired greatly, and then, the layout process is proceeded to.
Such a technology is disclosed in Japanese laid-open patent application No. 2000-231583 by NEC Corp. In this technology, when logic synthesis is performed considering a conventional floor-planning, replacing a logic cell with a high drive cell for delay adjustment is not performed, but a delay improvement is made by inserting a buffer for the adjustment automatically in consideration of the number of fan-out, from information on a temporary floor planning.
However, even when using the above-mentioned conventional technique, there is no guarantee of achieving timing convergence positively after wiring at a time of layout. Moreover, since a buffer for fan-out adjustment is inserted at a time of logic synthesis, wiring efficiency may become degraded at the time of layout.